Principal Interconnect Design Engineer
Core
Designing industry-leading CPU and interconnect IP, specifically TileLink interconnects and cache controllers, to drive RISC-V adoption in SOC designs.
Role type
Principal IC hardware design engineer (CPU/interconnect)
Builds
Massively customizable CPU and interconnect IP (TileLink, cache controllers, protocol bridges) for RISC-V based SoCs
Domain
Semiconductor / Chip Design / RISC-V Architecture
Deliverable
production ML models | product features | infrastructure
Required skills
Cache and cache coherency architecture, NoC and interconnect fabrics, Industry-standard bus protocols (AXI, AHB, APB, CHI, CXL, UCIe), Functional programming, Templated metaprogramming, Compiler infrastructure, Data modeling, RTL design (Verilog/System Verilog/VHDL), Test-driven development
Preferred skills
Scala/Chisel, Bluespec, RISC-V architecture, Git/Github, Jira, Confluence
Technologies
Chisel, Scala, FIRRTL, TileLink, System Verilog, Verilog, VHDL
Responsibilities
Architect and implement enhanced TileLink interconnects and cache controllers as RTL generators, Implement self-configuring RTL generators, Enhance designs for multi-core coherence and performance, Integrate design content into Chisel/FIRRTL framework, Perform initial sandbox verification and collaborate on verification test plans, Create and maintain technical documentation
Seniority
Principal, hands-on IC
