Hardware Design Integrity Engineer
Core
Debugging production system problems and delivering root cause analysis and fixes for high-speed networking hardware.
Role type
Senior Hardware Design Integrity Engineer
Builds
High-speed networking and Ethernet products for Enterprise campuses, hyperscaler datacenters, and AI clusters.
Domain
Networking hardware, high-speed PCB design, signal integrity
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Debugging networking hardware, 20+ layer board design, 50G+ signal handling, multi-phase DC/DC debugging, high-speed interface design (DDR, PCIe), low-speed signal design (I2C, SPI), signal integrity analysis, power integrity analysis, FPGA design (Verilog), script writing for log analysis, lab measurements
Preferred skills
Experience with component level or third party RCAs, test escape identification, developing new tests
Technologies
Verilog, PCIE analyzers, TDRs, VNAs, Bode plots, PDNs
Responsibilities
Deep dive into existing hardware design aspects (CPU/ASIC, power, SI, clocking, PCIE, optics, fab, components), work with sw & customer teams on high pressure escalations, write scripts to look for specific information in logs, make firmware/schematic/BOM/fab changes, perform lab measurements and debug, work with component/FA/ODM teams to identify fixes, identify test escapes, write and present root cause analysis for executives and customers
Seniority
Senior, hands-on IC
