Design Architect
Core
Lead the design of high-performance physical IP for industry-standard protocols, driving architecture from concept to RTL implementation while optimizing for power, performance, and area.
Role type
Senior IC Digital Design Architect (SerDes/Physical IP)
Builds
High-performance SerDes physical IP portfolios for industry-standard protocols
Domain
Semiconductor / Digital Design / SerDes
Deliverable
production ML models | product features
Required skills
Digital architecture, RTL implementation, synthesis and timing analysis, low-power design, DFT, verification strategy, embedded uC architecture, AI-assisted design flow
Preferred skills
Mixed-signal/analog design collaboration, scripting for design automation, knowledge of Serial standards (PCIe, USB, Ethernet), programming in System Verilog/Python/C++, revision control tools
Responsibilities
Define digital architecture and trade-offs for power/performance/area, drive micro-architecture to RTL implementation, collaborate with verification and analog teams on testing strategies and coverage, execute tool flows for IP quality control
Seniority
Senior, hands-on IC
