Physical Design CAD Engineer
Core
Developing physical design, synthesis, static timing analysis (STA), and logic equivalence methodologies for high-speed networking chips and System-on-Chips (SOCs) to ensure high throughput and low latency.
Role type
Senior IC Physical Design CAD Engineer
Builds
Networking silicon chips and SOCs
Domain
Semiconductor / Networking
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Python, Perl, Tcl, Make scripting; crosstalk delay and noise glitch analysis; electrical and manufacturing rule convergence; physical design optimization (placement, routing, cell sizing, buffering, logic restructuring); ECO implementation; process variation effect modeling; flow and tool methodology development
Preferred skills
Synthesis, place and route, STA EDA tools (Synopsys DC/FC/PT, Cadence Innovus/Tempus); methodology definition and flow ownership
Technologies
Synopsys Design Compiler, Formality, PrimeTime; Cadence Innovus, Tempus
Responsibilities
Develop physical design, synthesis, STA, and logic equivalence methodologies; collaborate with block owners, full chip STA engineers, and project managers for convergence; create unique solutions for state-of-the-art physical design problems; develop flow and tool methodologies for floorplan, power, clock distribution, P&R, timing analysis, closure, power/noise analysis, and back-end verification
Seniority
Senior, hands-on IC
