Principal Design Engineer - Physical Design
Core
Lead high-speed digital DDR PHY IP physical implementation and optimize design flows for cutting-edge semiconductor processes.
Role type
Principal Design Engineer (Physical Design)
Builds
High-performance digital PHY IP for advanced process nodes (TSMC 2nm/3nm/5nm/7nm/12nm, Samsung 2nm/4nm/5nm/7nm/8nm/10nm)
Domain
Semiconductor / Physical Design / High-Speed Digital
Deliverable
production ML models | product features
Required skills
Floorplan, CTS, STA, Physical verification, Power analysis, Scripting (Perl, C shell, TCL, Makefile, Python), EDA tools (Innovus, ICC, Calibre, Tempus, PrimeTime)
Preferred skills
Advanced design methodology for cutting-edge process nodes
Responsibilities
Complete project tasks for high-speed digital DDR PHY IP; develop scripts or tools to enhance PD design flow; solve design issues and provide flows to check and avoid similar issues; analyze and summarize PPA optimization methodologies and results; implement optimal design parameters and flows for different projects
Seniority
Principal, hands-on IC
