ASIC Design Engineer, STA
Required skills
Bachelor’s degree in Electrical or Computer engineering and 5+ years of ASIC Design experience, or Master's degree in Electrical or Computer Engineering and 3+ years of experience, or PhD + 0 years of experience, Experience with Verilog/SystemVerilog programming
Preferred skills
Prior STA experience, Strong written and verbal communication skills
Technologies
Verilog, SystemVerilog
Responsibilities
Closing timing at block, sub-chip, and full-chip levels, Performing quality checks such as setup, hold, transition, and noise, Handling ECO tasks, Developing methodologies, guidelines, and checklists to streamline STA work, Resolving design and flow issues, Driving execution to ensure progress and accuracy
Seniority
Not specified
Domain
ASIC Design, Static Timing Analysis (STA), Physical Design
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