ASIC Design Engineer, STA
Core
Develop methodologies, guidelines, and checklists for static timing analysis (STA) flow, resolve design and flow issues, and ensure convergence between PNR, Spice, and STA for web scale and service provider network silicon.
Role type
ASIC Design Engineer (Static Timing Analysis)
Builds
Unified silicon architecture for web scale and service provider networks
Domain
Semiconductor / ASIC Design
Deliverable
production ML models | product features | infrastructure
Required skills
Static Timing Analysis (STA), Verilog, SystemVerilog, Physical Design flow, Setup/Hold analysis, Noise analysis, ECO tasks
Preferred skills
Prior STA experience
Technologies
Verilog, SystemVerilog, PNR, Spice
Responsibilities
Develop STA methodologies and guidelines, Resolve design and flow issues, Drive execution for progress and accuracy, Perform quality checks (setup, hold, transition, noise), Handle ECO tasks
Seniority
Mid-Senior, hands-on IC
