Compute Subsystem Architect
Core
Define and build compute subsystem capabilities for next-generation ASIC and advanced Arm computing platform products, covering core configuration, cache architecture, and interconnect topology.
Role type
Senior IC Compute Subsystem Architect
Builds
Next-generation ASICs and advanced Arm computing platforms
Domain
Semiconductor / Arm Architecture / Chip Design
Deliverable
production ML models | product features | infrastructure
Required skills
CPU cluster architecture, CMN topology design, cache/SLC architecture, CHI coherency behavior, chiplet and 3D-IC partitioning, performance modeling, Arm Neoverse roadmap knowledge
Preferred skills
Packaging and interconnect interface definitions, multi-die scope engagement
Technologies
Arm Neoverse, CMN, CHI, 3D-IC, ASIC
Responsibilities
Architect compute subsystems (CPU cluster, L2/L3/SLC cache, coherent mesh fabric), own CMN topology recommendations, build CPU subsystem performance models, drive technology readiness with Arm, evaluate architectural implications of 3D-IC and chiplet splits, align design with product landing vehicles, prepare architecture specifications and present trade-offs
Seniority
Senior, hands-on IC
