SOC Timing Analysis (STA) Engineer ,HBM
Core
Own chip-level static timing sign-off and methodology development for next-generation High Bandwidth Memory (HBM) dies in sub-5nm nodes.
Role type
Senior IC Static Timing Analysis (STA) Engineer
Builds
High Bandwidth Memory (HBM) solutions for AI and ML applications
Domain
Semiconductor / Advanced Node Chip Design
Deliverable
production ML models
Required skills
Chip-level static timing analysis, Synopsys PrimeTime, Cadence Tempus, Multi-mode multi-corner (MMMC) analysis, On-chip variation (OCV/AOCV/POCV), Signal integrity and crosstalk analysis, SDC constraint development, Python/Tcl scripting, Post-silicon timing correlation
Preferred skills
Design-for-test (DFT) concepts, Liberty timing models, ECSM/CCS noise models, Agentic AI workflow development
Technologies
Synopsys PrimeTime, Cadence Tempus, Python, Tcl
Responsibilities
Own end-to-end chip-level static timing analysis and sign-off across all process corners and operating modes; Develop and validate comprehensive Synopsys Design Constraints (SDC) for clock domains, reset trees, and HBM interfaces; Drive timing closure at block, subsystem, and full-chip levels through critical path analysis and ECOs; Perform multi-mode, multi-corner timing analysis including CDC and application of on-chip variation derates; Lead signal integrity and crosstalk analysis and DFT timing analysis; Partner with RTL and architecture teams to provide early feedback on micro-architectural decisions and develop automation scripts; Perform post-silicon timing correlation and engage with EDA tool vendors; Define static timing analysis methods and standards and mentor junior engineers
Seniority
Senior, hands-on IC
