Physical Design Engineer
Core
Translate logical circuit designs into physical layouts, optimizing for area, power, and timing while ensuring manufacturing constraints are met.
Role type
Senior IC physical design engineer (Block/SoC level)
Builds
Physical layouts for integrated circuits at 10nm/7nm/5nm process nodes
Domain
Semiconductor hardware design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Physical Design, PnR tools (ICC2/Innovus), SDC, STA, Equivalence checking, Unix/Linux, SKILL, Shell/Python scripting
Preferred skills
Flow automation, Tapeout sign-off experience
Technologies
Cadence Encounter, Synopsys ICC2, ICC2, Innovus
Responsibilities
Perform placement, routing, and clock tree synthesis; collaborate with timing and verification teams to resolve design issues; ensure timing and manufacturing constraints are met before tape-out.
Seniority
Senior, hands-on IC