Mixed Signal Digital Design Lead
Core
Lead the development of digital control infrastructures for advanced clocking sub-systems (PLLs, FLLs, and DLLs).
Role type
Senior IC mixed-signal digital design lead
Builds
Digital control logic for clocking IPs
Domain
Semiconductor / ASIC Design
Deliverable
production ML models | product features
Required skills
SystemVerilog RTL, digital ASIC design, architecture definition, state machine design, CDC/RDC sign-off methodology, cross-functional leadership
Preferred skills
Experience with N5/N3P technology nodes, DVFS controller design, fractional-N delta-sigma modulators
Technologies
SystemVerilog, PLLs, FLLs, DLLs
Responsibilities
Own architectural definition and RTL implementation of digital logic for clocking IPs; Design complex digital control loops and state machines for adaptive calibration; Serve as primary bridge to Analog Circuit Designers to translate specs into digital architectures; Partner with Verification Teams on Mixed-Signal Verification and Real Number Modeling strategies; Collaborate with Physical Design Teams on floorplanning and noise protection; Enforce full-chip CDC and RDC sign-off methodology.
Seniority
Senior, hands-on IC
