SoC Timing (Static Timing Analysis/STA) Engineer, HBM
Core
Own end-to-end chip-level static timing analysis and sign-off for next-generation die, ensuring timing integrity across all modes and corners from initial design through tape-out.
Role type
Senior IC Static Timing Analysis (STA) Engineer
Builds
High Bandwidth Memory (HBM) solutions for AI and ML applications using Through Silicon Via (TSV) technology
Domain
Semiconductor / Advanced Node SoC Design
Deliverable
production ML models
Required skills
Chip-level static timing analysis ownership, Synopsys PrimeTime/Cadence Tempus expertise, multi-mode multi-corner (MMMC) analysis, SDC constraint authoring, Python/Tcl scripting, signal integrity analysis, ECO management, mentorship
Preferred skills
HBM/DRAM design experience, chiplet/3D IC design knowledge, DFT timing expertise, Liberty timing models familiarity, Agentic AI workflow development
Technologies
Synopsys PrimeTime, Cadence Tempus, Python, Tcl, SDC, TSV, HBM
Responsibilities
Own end-to-end chip-level static timing analysis and sign-off; Develop and validate Synopsys Design Constraints (SDC); Drive timing closure at block, subsystem, and full-chip levels; Perform multi-mode, multi-corner (MMMC) analysis; Lead signal integrity and crosstalk analysis; Build and maintain STA automation flows using Python and Tcl; Conduct post-silicon timing correlation; Mentor junior engineers and collaborate cross-functionally
Seniority
Senior, hands-on IC
