Senior ASIC Timing Engineer, DFT
Core
Drive timing analysis and closure for DFT logic across all hierarchical levels (block/cluster/full-chip) on NVIDIA chips including GPUs, CPUs, DPUs, LPUs, and SoCs.
Role type
Senior IC ASIC Timing Engineer (DFT)
Builds
GPU, CPU, DPU, LPU, and SoC chips
Domain
Semiconductor / ASIC Design
Deliverable
production ML models | product features | infrastructure
Required skills
Static Timing Analysis (STA), timing convergence at full-chip/sub-chip level, ECO implementation, timing constraint development, industry standard timing convergence tools
Preferred skills
DFT logic expertise, scan and iJTAG timing closure, domain-specific STA (Serdes, Processor, IO, SMVA), methodology and workflow development
Technologies
Advanced technology nodes, industry standard timing convergence tools
Responsibilities
Drive timing analysis and closure for DFT logic; collaborate with PD, DFX, and Clocks teams to develop timing closure strategies; implement ECOs for timing and power convergence; improve workflows through automation and standardization
Seniority
Senior, hands-on IC
