Junior Physical Design Engineer
Core
Junior Physical Design Engineer establishing backend execution culture and technical standards for complex semiconductor chips enabling AI scale-up and scale-out connectivity.
Role type
Junior IC physical design engineer (backend)
Builds
Custom connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, and UALink for hyperscalers
Domain
Semiconductor / AI Infrastructure / High-speed connectivity
Deliverable
production ML models
Required skills
RTL-to-GDS flow, floorplanning, placement, routing, Clock-Tree Synthesis (CTS), Static Timing Analysis (STA), DRC, LVS, EMIR analysis, Logic Equivalence Checking (LEC), TCL/Python scripting, advanced process nodes (7nm and below)
Preferred skills
full-chip implementation, Power/Noise analysis (SI/PI), Design-for-Test (DFT), high-speed interface designs, Synopsys Fusion Compiler/ICC2, Cadence Innovus
Technologies
Synopsys Fusion Compiler, ICC2, Cadence Innovus, CXL, Ethernet, NVLink, PCIe, UALink
Responsibilities
Establish local execution culture and technical standards for the founding Backend team in Israel; own physical implementation journey from synthesis through signoff; drive Timing signoff, Physical Verification, and Reliability analysis; participate in defining Backend methodologies and tool automation; collaborate with Architecture, Design, and DFT teams
Seniority
Junior, hands-on IC
