Tech Lead ASIC Design Engineer
Core
Lead the architecture, RTL design, and implementation of complex digital IPs and SoC subsystems for next-generation AI infrastructure connectivity products.
Role type
Senior IC ASIC Design Engineer (Digital/SoC)
Builds
Custom connectivity silicon (CXL, PCIe, Ethernet) for hyperscalers and system OEMs
Domain
Semiconductor / AI Infrastructure / High-Speed Interconnects
Deliverable
production ML models | product features
Required skills
Verilog/System Verilog RTL design, SoC integration, high-speed interface protocols, ASIC design cycle ownership, synthesis, lint, CDC/RDC, STA, debugging
Preferred skills
CXL, PCIe, Ethernet MAC/PCS, AXI-based SoC architecture, DMA engines, packet processing pipelines, cache coherency protocols, memory controllers, low-power design, DFT
Technologies
Synopsys Design Compiler, Cadence Genus, SpyGlass, Git, Python, Tcl, Perl, Shell
Responsibilities
Define microarchitecture and review functional specifications; develop verification strategies and debug design issues; resolve timing, power, and congestion challenges; drive RTL optimization and sign-off activities; debug post-silicon issues
Seniority
Senior, hands-on IC with technical leadership
