ASIC Physical Design Engineer
Core
Design, test, and deploy advanced hardware for ultra low latency trading, networking, and research infrastructure.
Role type
Senior ASIC Physical Design Engineer (full-stack chip design)
Builds
Custom ASIC chips for trading and infrastructure systems
Domain
Fintech hardware / ASIC design
Deliverable
production ML models | product features
Required skills
End-to-end physical design flow ownership, RTL design and verification, cross-domain design reasoning, hardware-aware software engineering, high-level programming (Python/C++/Haskell), modern PD tools expertise
Preferred skills
Experience with Hardcaml/OCaml, toolchain development
Technologies
Hardcaml, OCaml, Python, C++, Haskell, modern EDA tools
Responsibilities
Lead physical design flows from floorplanning to timing closure, collaborate across front-end/back-end boundaries, optimize hardware design processes using software techniques
Seniority
Senior, hands-on IC
