Principal DFT Engineer (Silicon Engineering)
Core
Lead implementation and optimization of DFT architectures for next-generation ASICs deployed in space and ground infrastructures to enable global connectivity.
Role type
Principal DFT Engineer (Silicon Engineering)
Builds
Next-generation ASICs for Starlink satellite and ground systems
Domain
Aerospace / Semiconductor Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Scan insertion, ATPG methodologies, memory BIST, logic BIST, Siemens Tessent tools, Perl, Python, Tcl, C+, RTL connectivity debugging, clock domain crossing analysis, power optimization, UPF, formal verification, DRC rule checking, ATE tester integration
Preferred skills
SOC DFT execution leadership, Verilog/SystemVerilog implementation, advanced silicon process nodes familiarity
Technologies
Siemens Tessent, Perl, Python, Tcl, C+, Verilog, SystemVerilog, UPF
Responsibilities
Lead implementation and optimization of DFT architectures including scan insertion, compression/decompression logic, and BIST; Own ATPG tools and methodologies for fault models and test flows; Evaluate design readiness for scan insertion via RTL and physical design DRC tools; Integrate and verify DFT fabrics and IP within subsystems; Run and debug non-timing and SDF annotated gate level simulations; Develop test scripts, automate processes, and analyze data
Seniority
Principal, hands-on IC with strategic oversight