Staff Digital Design Engineer
Core
Lead architecture, implementation, and integration of digital subsystems for Automotive Ethernet PHY products (10BASE‑T1S, 100BASE‑T1, 1000BASE‑T1, and multi‑gig automotive SerDes technologies), driving digital micro-architecture, state machines, PCS functionality, and safety mechanisms.
Role type
Staff Digital Design Engineer (Automotive Ethernet PHY)
Builds
Automotive Ethernet PHY chips (10BASE‑T1S, 100BASE‑T1, 1000BASE‑T1, multi‑gig SerDes)
Domain
Automotive semiconductor / High-speed digital communication
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Verilog/SystemVerilog RTL design, High-speed digital logic, State machines, Control logic, IEEE 802.3 Ethernet PCS, Link training, System control flows, Synthesis, STA, CDC/RDC methodology, Digital subsystem micro-architecture, Safety mechanisms (BIST, LBIST/MBIST), Error detection schemes, Diagnostic monitors, Timeout recovery logic, Watchdogs, Fault reporting, System-level partitioning, Processor based SoC design
Preferred skills
Automotive Ethernet standards (10BASE‑T1S, 100BASE‑T1, 1000BASE‑T1, 10GBASE‑T1), PHY firmware-driven initialization, Debugging with logic/protocol analyzers, Post-silicon validation, Safety-critical digital logic designs
Technologies
Verilog, SystemVerilog, IEEE 802.3, ISO 26262, AEC‑Q100, MII, RMII, RGMII, GMII, XGMII
Responsibilities
Define and own digital subsystem micro-architecture for Automotive Ethernet PHYs, Develop high-quality RTL for control, datapath, and protocol logic, Translate system requirements and IEEE 802.3 specifications into robust digital designs, Ensure compliance with Automotive Ethernet standards, ISO 26262, and AEC‑Q100 expectations, Lead feasibility studies, power/performance trade-offs, and digital architecture exploration, Work with mixed-signal teams to define control interfaces, calibration engines, and digital-analog interaction models
Seniority
Staff, hands-on IC with technical leadership
