IP Design Director
Core
Lead the design and implementation of high-performance digital IP and full-chip solutions for rack-scale AI connectivity infrastructure.
Role type
Senior IC IP Design Director (Digital Design)
Builds
Custom connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies for hyperscalers.
Domain
Semiconductor hardware design, AI infrastructure, high-performance computing
Deliverable
production ML models | product features
Required skills
RTL development, micro-architecture, timing closure, UVM-based verification, System Verilog/Verilog, Python/Perl scripting, silicon bring-up, post-silicon debug, PCIe design, processor IP integration (ARM/ARC), advanced node design (≤16nm), DMA engine design, firmware interaction
Preferred skills
Secure boot implementation, RISC-V subsystems, PAD design, DFT, floor planning, NIC/switch/storage product development, CI/CD design workflows
Technologies
Synopsys, Cadence, UVM, System Verilog, Verilog, Python, Perl, ARM, ARC, RISC-V, PCIe, CXL, NVLink, UALink
Responsibilities
Design and implement high-performance digital solutions including RTL development and synthesis; Collaborate on IP integration for processor IPs and peripherals; Own block-level and full-chip designs from architecture to GDS at nodes ≤ 16nm; Ensure timing closure and oversee pre- and post-silicon debug; Utilize Synopsys/Cadence tools for first-pass silicon success.
Seniority
Senior, hands-on IC
