Physical Design Engineer, Synthesis and Implementation
Core
Own RTL-to-gate synthesis and QoR convergence for complex digital blocks and hierarchical partitions while supporting physical implementation from floorplanning through routing and timing closure.
Role type
Senior IC physical design engineer (synthesis and implementation)
Builds
High-speed communication devices (Networking Silicon)
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features
Required skills
RTL-to-gate synthesis, QoR optimization, place-and-route flow, timing analysis, Python, Perl, Tcl, Make
Preferred skills
Advanced process node experience, automation of design flows
Technologies
Synopsys Fusion Compiler, Cadence Genus
Responsibilities
Optimize synthesis strategies and constraints to meet performance, power, and area targets; Analyze design bottlenecks and QoR regressions; Automate design setup, execution, reporting, and issue triage
Seniority
Mid-level, hands-on IC