Senior ASIC Design Engineer
Core
Design and implement micro-architecture and build implementation for Network-on-Chip (NOC) and interconnect crossbars in high-performance SoCs and GPUs.
Role type
Senior ASIC Design Engineer (Interconnect/NoC)
Builds
High-performance SoCs and GPUs for consumer graphics, autonomous vehicles, and AI
Domain
Semiconductor / Hardware Design / AI Infrastructure
Deliverable
production ML models | product features
Required skills
Micro-architecture design, RTL build, Verilog/System-Verilog, Computer Architecture, ASIC flow (synthesis, timing, ECO), Debugging, Arbitration logic, Interconnect routing, Virtual channels
Preferred skills
Experience with switches, bus protocols, synchronization, deadlock avoidance
Technologies
Verilog, System-Verilog, RTL, Logic Synthesis, Timing Analysis, ECO
Responsibilities
Micro-architect features to meet area, performance, and power requirements; Deliver fully verified builds with verification engineers; Deliver synthesis/timing clean builds; Collaborate with architects, verification, software, and physical build engineers
Seniority
Senior, hands-on IC
