Senior STA Timing Engineer
Core
Develop and validate timing constraints for advanced chip designs to ensure accurate and reliable test and verification of complex integrated circuits.
Role type
Senior IC STA Timing Engineer
Builds
Static timing analysis (STA) flows and validation processes for silicon design
Domain
Semiconductor / Integrated Circuit Design
Required skills
Static Timing Analysis (STA), SDC creation and validation, PrimeTime, scripting (Perl/TCL/Python/Makefile), timing exception handling, DFT modes (scan shift/capture, ATPG capture)
Preferred skills
Synopsys GCA/TCM, Synopsys Fusion Compiler, Tessent DFT insertion, DFT mode debugging (BIST)
Technologies
PrimeTime, Synopsys Fusion Compiler, Tessent, Perl, TCL, Python, Makefile
Responsibilities
Own creation and validation of timing constraints at block, sub-chip, and full-chip levels; perform quality checks for duplicated constraints and unconstrained endpoints; develop methodologies and checklists for STA workflows; collaborate on resolving timing and design flow issues; implement and maintain SDC flows.
Seniority
Senior, hands-on IC
