Senior STA Timing Engineer
Core
Develop and validate timing constraints for advanced chip designs to ensure accurate test and verification of complex integrated circuits.
Role type
Senior IC STA Timing Engineer
Builds
Static timing analysis (STA) flows and validation processes for silicon designs
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Static Timing Analysis (STA), SDC creation and validation, PrimeTime, scripting (Perl/TCL/Python/Makefile), block/sub-chip/full-chip constraint development, timing exception handling
Preferred skills
DFT mode debugging (scan shift/capture, BIST), Synopsys GCA/TCM/PrimeTime, Synopsys Fusion Compiler, Tessent DFT insertion
Technologies
PrimeTime, Synopsys Fusion Compiler, Tessent, Perl, TCL, Python, Makefile
Responsibilities
Own creation and validation of timing constraints at block, sub-chip, and full-chip levels in test modes; Perform quality checks to identify duplicated constraints and verify unconstrained endpoints; Develop methodologies and checklists to streamline STA workflows; Collaborate with cross-functional teams to resolve timing and design flow issues; Implement and maintain SDC flows and validation processes
Seniority
Senior, hands-on IC
