CPU Power-Management Design Engineer
Core
Designing power management, reset, and clocking solutions for RISC-V CPU cores and SoC IP to serve high-performance, data-intensive applications.
Role type
Senior IC hardware design engineer (CPU power/clock/reset micro-architecture)
Builds
Industry-leading RISC-V CPU and SoC IP blocks
Domain
Semiconductor / Chip Design / RISC-V Architecture
Deliverable
production ML models | product features | infrastructure
Required skills
CPU/SoC clocking and reset design, Power Management Unit (PMU) design, Dynamic voltage and frequency scaling (DVFS), RTL design in Verilog/SystemVerilog, Hardware verification planning, Physical design optimization, DFT and error handling, Object-oriented or functional programming
Preferred skills
AMBA Interconnect Protocols (AXI, AHB, APB), Low Power Protocol Interfaces (P-channel, Q-channel), Hardware DSLs (Scala/Chisel, Bluespec), RISC-V architecture knowledge
Technologies
Verilog, SystemVerilog, Spyglass, Git, Jira, Confluence
Responsibilities
Define power management requirements with architecture team, Architect and implement core clocking/reset/power solutions, Develop microarchitecture specifications and documentation, Execute verification test plans for power/clock/reset logic, Collaborate with physical implementation for frequency/area/power goals, Enable and optimize power management features with software team
Seniority
Mid-Senior, hands-on IC
