Logic Design Engineer
Core
Designing micro-architecture and RTL for large-scale programmable silicon devices that power Cisco's future routing portfolio.
Role type
Senior IC logic design engineer (RTL/micro-architecture)
Builds
Programmable silicon chips for high-performance networking routers
Domain
Semiconductor / Networking Infrastructure
Deliverable
production ML models | product features
Required skills
RTL design (Verilog/SystemVerilog), micro-architecture specification, timing analysis, UVM, functional verification, debug and root-cause analysis
Preferred skills
MATLAB simulations, bit-exact modeling, mixed-signal systems, Clock Domain Crossing (CDC)
Technologies
Verilog, SystemVerilog, UVM, MATLAB
Responsibilities
Write and review micro-architecture specifications; Implement RTL to meet timing, performance, and power requirements; Contribute to full chip integration and timing methodology; Collaborate with verification engineers to resolve bugs; Work with physical design teams to close timing and PnR issues; Perform debug and post-silicon validation
Seniority
Senior, hands-on IC
