Staff RTL Design Engineer - CPU Midcore
Core
Architect, design, and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
Role type
Staff RTL Design Engineer (CPU Midcore)
Builds
RISC-V CPU cores and hardware IP
Domain
Semiconductor / CPU Microarchitecture
Deliverable
production ML models | product features | infrastructure
Required skills
CPU RTL design, Verilog/System Verilog/VHDL, Chisel, functional programming, templated metaprogramming, compiler infrastructure, data modeling, test-driven development
Preferred skills
Scala/Chisel, Bluespec, RISC-V architecture, UVM, Git/Github, Jira, Confluence
Technologies
Chisel, FIRRTL, Verilog, System Verilog, VHDL, Scala, Bluespec, UVM
Responsibilities
Architect and design new features and ISA extensions in CPU core generators; Integrate design content into Chisel/FIRRTL framework; Perform initial sandbox verification and create verification test plans; Collaborate with physical implementation team for optimization; Work with performance modeling team for optimization; Develop microarchitecture specifications and documentation.
