Physical Design Engineer
Core
Drive RTL-to-GDSII implementation and physical design closure for next-generation in-memory computing chips.
Role type
Physical Design Engineer (IC Design)
Builds
High-performance AI hardware chips for edge-to-cloud computing
Domain
Semiconductor / AI Hardware
Deliverable
production ML models
Required skills
RTL-to-GDSII flow, floorplanning, placement, CTS, routing, physical verification (LVS/DRC/ERC), Static Timing Analysis (STA), Power Integrity analysis (IR-drop, EM), multi-corner multi-mode (MCMM) closure, low-power design (UPF/CPF)
Preferred skills
Python/Tcl scripting, AI/ML-based EDA automation, predictive PPA analysis
Technologies
Innovus, 3nm process nodes
Responsibilities
Execute high-performance design closure focusing on PPA targets, perform comprehensive timing closure including signal integrity and crosstalk analysis, conduct IR-drop and EM checks, develop and integrate AI/ML-based automation scripts to optimize physical design flow
Seniority
Mid-level IC Engineer (2-4 years experience)