Technical Manager – NPU Physical Design
Core
Leading physical design flow execution for semiconductor chips, managing synthesis, placement, routing, and signoff to ensure tapeout-quality designs.
Role type
Senior IC physical design manager
Builds
Integrated circuit chips
Domain
Semiconductor / Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL synthesis, floorplanning, placement, clock tree synthesis, routing, physical verification, Static Timing Analysis (STA), EMIR, Physical Verification (PV), project management, team leadership, EDA tool expertise
Preferred skills
Cross-functional collaboration, technical mentoring, risk mitigation, industry trend analysis
Technologies
EDA tools, synthesis tools, PNR tools, verification tools
Responsibilities
Lead RTL synthesis, floorplanning, placement, clock tree synthesis, routing, and physical verification tasks; Manage signoff activities including STA, EMIR, and PV; Collaborate with cross-functional teams (DFT, RTL, STA, Packaging); Plan, monitor, and execute project timelines and milestones; Guide and mentor engineering teams; Troubleshoot design challenges and communicate risks; Interface with EDA vendors and document processes
Seniority
Senior, hands-on IC
