Senior RTL Engineer/Lead
Core
Own micro-architecture, RTL development, integration, and synthesis for complex IP and ARM CPU subsystems.
Role type
Senior RTL Design Engineer / Lead
Builds
Complex IP blocks and ARM CPU subsystems
Domain
Semiconductor, SoC design, ARM architecture
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Micro-architecture definition, RTL coding and integration, Synthesis, Lint/CDC/LEC/equivalence checks, Timing constraint generation, Test plan definition, Debugging and scripting
Technologies
ARM, RTL, Synthesis tools, Lint, CDC, LEC
Responsibilities
Define micro-architecture for complex IP blocks and ARM CPU subsystems based on high-level specifications. Develop high-quality RTL (coding and integration) and perform synthesis for complex IP and CPU subsystems. Run RTL quality checks (e.g., Lint, CDC, LEC/equivalence checks) and ensure RTL is robust, reusable, and signoff-ready. Generate and refine timing constraints; collaborate with Physical Design teams to ensure RTL meets timing and implementation goals. Work with DV teams to define test plans, review coverage, and thoroughly verify RTL functionality. Collaborate with DFT teams to help improve test coverage and support DFT insertion requirements. Partner with worldwide cross-functional teams to align on specifications, interfaces, and delivery milestones. Use strong debugging and scripting skills to analyze issues, automate flows, and improve design productivity.
Seniority
Senior, hands-on IC
