Senior IP Design Engineer
Core
Build high-level architectural models and quality digital designs for Dynamic Voltage & Frequency Scaling (DVFS) IP to evaluate architectures, identify performance bottlenecks, and optimize power/performance in High-Performance Compute (HPC) products.
Role type
Senior IC IP Design Engineer (DVFS/Power Management)
Builds
DVFS IP blocks, clock delivery networks (CDN), and power delivery networks (PDN) for CPU/GPU/NPU
Domain
Semiconductor / SoC Design / Power Management
Deliverable
production ML models | product features
Required skills
SystemVerilog RTL, architectural modeling, RTL signoff (LINT, CDC, CLP), timing analysis, power analysis, SDC/UPF, collaboration with verification and physical design teams
Preferred skills
HPC product design experience, clock network design, power network design
Technologies
SystemVerilog, SDC, UPF
Responsibilities
Build high-level architectural models to evaluate new architectures and design trade-offs; Create quality digital designs using SystemVerilog RTL; Conduct RTL sign-off checks including LINT, CDC, and CLP; Collaborate with verification teams for block-level and system-level verification; Supply collateral for physical design including SDC/UPF and collaborate on timing critical path and power analysis
Seniority
Senior, hands-on IC
