SOC Physical Design and STA Methodology Engineer
Core
Develop production-grade PnR and STA signoff flows, automation utilities, and methodology best practices for SoC physical design at advanced nodes.
Role type
Senior IC physical design methodology engineer
Builds
Production-grade PnR flows, STA signoff flows, and automation utilities for partition and full-chip designs
Domain
Semiconductor / SoC Physical Design / Advanced Node (3nm, 2nm)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (PnR/STA flows)
Required skills
SoC Physical Design, PnR flow development, STA fundamentals, EDA scripting (Python, Tcl, Perl, UNIX shell), Synopsys tools (Fusion Compiler, PrimeTime, ICV, Formality), Cadence tools (Innovus, Genus, Voltus, Tempus), Power planning, Timing debug, OCV/POCV derates, PVT corners, ECO flows, Low power design (UPF, power gating, voltage islands), DTCO, Formal verification (LEC), Hierarchical STA
Preferred skills
AI-driven optimization tools (DSO.ai, Cerebrus), Advanced ECO tools (Tweaker, PrimeClosure), Library and cell architecture optimization
Technologies
Python, Tcl, Perl, UNIX shell, Synopsys Fusion Compiler, Synopsys PrimeTime, Synopsys ICV, Synopsys Formality, Cadence Innovus, Cadence Genus, Cadence Voltus, Cadence Tempus, UPF, SDC, DSO.ai, Cerebrus, Tweaker, PrimeClosure
Responsibilities
Develop production-grade PnR flows for partition and Chip Top level designs including power planning, placement, optimization, and routing; Develop automation utilities for PnR execution, signoff analysis, and ECO implementation; Debug, enhance, and release PnR and STA signoff flows for multiple projects and process nodes; Support partition and full-chip design teams on complex convergence issues, timing closure, and DRC fixing; Document flows, create regression tests, and train design teams on methodology best practices
Seniority
Senior, hands-on IC
