ASIC Engineering Lead
Core
Lead end-to-end physical implementation of high-complexity silicon blocks from RTL to tape-out, ensuring production-ready design delivery for innovative networking technology.
Role type
Senior ASIC Engineering Lead (Physical Design)
Builds
High-complexity silicon blocks for networking chips
Domain
Semiconductor / Networking
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Deep submicron CMOS design, RTL to GDSII flow, block-level synthesis, place-and-route, timing closure, PPA optimization
Preferred skills
EM/IR and ESD analysis, Tcl/Python/Shell scripting, technical mentorship, global team collaboration
Technologies
Synthesis tools, Place-and-route tools, Timing closure tools
Responsibilities
Lead physical implementation from RTL to tape-out, resolve complex implementation challenges, advance physical design methodologies, provide technical direction to peers
Seniority
Senior, hands-on IC