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ASIC Engineering Lead

Armenia💼 Full-time🗓 2026-04-02 → 2026-07-31

Core

Lead end-to-end physical implementation of high-complexity silicon blocks from RTL to tape-out, ensuring production-ready design delivery for innovative networking technology.

Role type

Senior ASIC Engineering Lead (Physical Design)

Builds

High-complexity silicon blocks for networking chips

Domain

Semiconductor / Networking

Deliverable

production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work

Required skills

Deep submicron CMOS design, RTL to GDSII flow, block-level synthesis, place-and-route, timing closure, PPA optimization

Preferred skills

EM/IR and ESD analysis, Tcl/Python/Shell scripting, technical mentorship, global team collaboration

Technologies

Synthesis tools, Place-and-route tools, Timing closure tools

Responsibilities

Lead physical implementation from RTL to tape-out, resolve complex implementation challenges, advance physical design methodologies, provide technical direction to peers

Seniority

Senior, hands-on IC

Rewrite
## Responsibilities * Lead the end-to-end physical implementation of high-complexity silicon blocks from RTL to tape-out to ensure production-ready design delivery. * Apply deep expertise in synthesis, place-and-route, and timing closure to meet stringent performance, power, and area (PPA) goals. * Collaborate with global frontend, IP, and CAD teams to resolve complex implementation challenges and ensure seamless system-level integration. * Advance physical design methodologies by leading technical investigations and proposing improvements to streamline development flows. * Provide technical direction to peers to foster an innovative engineering environment that delivers impactful networking solutions. ## Requirements * Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field. * Minimum of 8 years of experience in ASIC design, physical implementation, and verification. * Proven expertise in deep submicron CMOS technologies. * Extensive knowledge of the full design cycle from RTL to GDSII. * Demonstrated mastery in block-level synthesis, place-and-route, and timing closure. * Excellent verbal and written communication skills in English. ## Nice to Have * Direct experience with EM/IR and ESD analysis, including debugging and solution development. * Proficiency in scripting languages such as Tcl, Python, or Shell to improve design flow efficiency. * Proven ability to mentor team members and foster a collaborative environment. * Experience collaborating with global teams and external vendor partners. ## Benefits * Join Cisco’s CHG Team in Armenia, a team at the forefront of physical design for the globally recognized Silicon One brand. * Work on cutting-edge networking chips in a dynamic, global environment. * Collaborate with a team of experts dedicated to redefining the boundaries of what is possible in silicon. * Be part of a company revolutionizing how data and infrastructure connect and protect organizations in the AI era. * Access to a worldwide network of doers and experts with limitless opportunities to grow and build.
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