Physical Design Intern
Core
Implement tool flows, develop CAD methodologies, and generate scripts for ASIC physical design tasks including place and route, timing closure, and backend activities.
Role type
Physical Design Intern (ASIC)
Builds
ASIC chips for data infrastructure (enterprise, cloud, AI, carrier architectures)
Domain
Semiconductor / VLSI Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
ASIC physical design, place and route, timing closure, static timing analysis, crosstalk analysis, design for testing, synthesis, physical synthesis, scripting (TCL, Unix shell), Python (optional), CAD tools (Synopsys, Cadence, Mentor), design rule learning, optimization (timing/area/power), technical documentation
Preferred skills
Experience with Synopsys, Cadence, or Mentor tools
Technologies
TCL, Unix shell, Python, Synopsys, Cadence, Mentor
Responsibilities
Implement block-level layout and perform timing closure; Conduct static timing and crosstalk analysis; Perform design for testing analysis; Execute synthesis and physical synthesis; Learn design rules for advanced technology nodes; Optimize designs for timing, area, and power; Write thorough documentation; Present and defend decisions and results to the team
Seniority
Intern