Senior Staff Power Performance Architect Accelerator Design
Core
Pre-silicon power estimation and performance optimization for AI accelerator blocks using RTL and physical design analysis.
Role type
Senior Staff Power Performance Architect (Accelerator Design)
Builds
Architectural power estimation tools for AI workloads and performance monitoring/boosting features for silicon.
Domain
Semiconductor hardware design, AI accelerators, IC design flow
Deliverable
production ML models | product features | infrastructure
Required skills
IC design flow (Arch to HVM), RTL design, physical design, power estimation, EDA tools, TCL, Python, algorithmic thinking
Preferred skills
TDP/PMAX/EDP metrics, DFS/DFVS/AFS/AVFS, PDN/resonance/droop analysis
Technologies
Leading edge CAD tools, semiconductor process technologies
Responsibilities
Perform pre-silicon power estimation for RTL and physical design blocks; collaborate with front-end and DV engineers to identify power activity windows; build architectural power estimation tools for AI workloads; integrate feedback into design to optimize power and performance; design micro-architecture and RTL with power/performance verification; implement performance enabling and power saving functions; participate in silicon bring-up and validation
Seniority
Senior Staff, hands-on IC architect
