Senior Staff Physical Design Architect (Flow & ML Automation)
Core
Architect the physical implementation backbone for next-generation, high-speed CPU cores using automated, ML-driven methodologies to optimize Power, Performance, and Area (PPA) on advanced process nodes.
Role type
Senior Staff Physical Design Architect (Flow & ML Automation)
Builds
High-frequency CPU cores (3GHz+) on N3/N2 nodes
Domain
Semiconductor / Chip Design / VLSI
Deliverable
production ML models
Required skills
Physical Design, RTL-to-GDS Flow, ML-driven optimization, EDA tool integration, Hierarchical floor planning, PPA modeling, Python/Tcl/Perl scripting, Timing closure, IR drop, Electromigration
Preferred skills
TSMC N2 experience, Synopsys DSO.ai deployment
Technologies
Synopsys Fusion Design Platform, IC Compiler II, PrimeTime, DSO.ai
Responsibilities
Architect and deploy RTL-to-GDS recipes; Lead integration of AI/ML optimization tools; Engage with EDA partners to influence tool roadmaps; Define global floor planning and integration strategies; Design robust build systems and automated dashboards; Perform early-stage PPA estimation and pathfinding.
Seniority
Senior Staff, hands-on IC
