Senior Staff Physical Design Architect (Flow & ML Automation)
Core
Architect the physical implementation backbone for next-generation high-speed CPU cores using ML-driven methodologies to optimize Power, Performance, and Area (PPA) on advanced nodes.
Role type
Senior Staff Physical Design Architect (Flow & ML Automation)
Builds
High-frequency CPU cores for data-intensive applications
Domain
Semiconductor chip design, VLSI, Advanced Process Nodes (N3/N2)
Deliverable
production ML models | product features
Required skills
Physical Design (RTL-to-GDS), High-speed CPU implementation (3GHz+), TSMC N3 process, Synopsys Fusion Design Platform, AI/ML design space optimization, Python/Tcl/Perl scripting, Timing closure, IR drop, Electromigration, Crosstalk analysis
Preferred skills
TSMC N2 process experience
Technologies
Synopsys DSO.ai, Fusion Compiler, IC Compiler II, PrimeTime
Responsibilities
Architect and deploy RTL-to-GDS recipes for high-frequency CPUs; Integrate and scale AI/ML optimization tools; Engage with EDA partners to influence tool roadmaps; Define global floor planning and integration strategies; Design robust build systems and automated dashboards; Perform early-stage PPA estimation and pathfinding.
Seniority
Senior Staff, hands-on IC
