Senior ASIC Design Engineer - NOC IP
Core
Designing micro-architecture and RTL for memory subsystem components in Graphics Processors.
Role type
Senior IC ASIC Design Engineer (Memory Subsystem IP)
Builds
Memory subsystem components for Graphics Processors
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features
Required skills
RTL design, Verilog, ASIC design flow, logic synthesis, timing analysis, DFT, floor-planning, ECO, bring-up & lab debug
Preferred skills
Memory subsystem or network interconnect IP design, FPGA prototyping, Python/Perl/shell scripting, leading small teams
Technologies
VCS, Debussy, GDB
Responsibilities
Own micro-architecture and RTL development of design modules; Micro-architect features to meet performance, power and area requirements; Work with HW architects to define critical features; Collaborate with verification teams to verify the correctness of implemented features; Co-operate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable; Interact with FPGA and S/W teams to prototype the design and ensure that S/W is tested; Work on post-silicon verification and debug.
Seniority
Senior, hands-on IC
