Senior Physical Design Engineer
Core
Designing high-speed communication chips with a focus on optimizing power, area, and performance through full RTL-to-GDS physical design flows.
Role type
Senior Physical Design Engineer (Networking Silicon)
Builds
High-throughput, low-latency networking silicon chips
Domain
Semiconductor / Networking / Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL2GDS flows, PNR, STA, physical verification, timing closure, power and noise analysis, place and route, partitioning, unit-level technical leadership
Preferred skills
Experience with high cell count and high-speed (HS) blocks
Technologies
Synopsys, Cadence
Responsibilities
Perform physical design of blocks and top-levels under challenging constraints; resolve complex timing and congestion problems; execute full RTL2GDS development including synthesis, power/clock distribution, place and route, timing closure, and physical verification; act as a technical leader and focal point at the partition/unit level
Seniority
Senior, hands-on IC
