Senior Engineer
Core
Senior Engineer leading physical design activities for SOC chips, covering floor-planning, placement, routing, verification, and timing closure.
Role type
Senior IC physical design engineer (SOC)
Builds
System-on-Chip (SOC) physical designs
Domain
Semiconductor / VLSI Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
floor-planning, partitioning, placement, clock tree synthesis, routing, physical verification (LVS/DRC/ERC/Antenna), equivalence checks, static timing analysis (STA), crosstalk delay analysis, noise analysis, power optimization, timing and functional ECO implementation, congestion resolution, formal verification
Preferred skills
experience with Innovus, Encounter, ICC, Caliber, LEC, Primetime
Responsibilities
Perform block-level floor-planning, partitioning, placement, clock tree synthesis, and routing; execute physical verification (LVS/DRC/ERC/Antenna); conduct equivalence checks, STA, crosstalk, noise, and power optimization; implement timing and functional ECOs; resolve congestion and achieve timing closure; guide team members on problem-solving
Seniority
Senior, hands-on IC