Staff Design Engineer
Core
Staff Design Engineer responsible for SOC physical design activities including floor-planning, partitioning, placement, clock tree synthesis, routing, and physical verification.
Role type
Staff IC physical design engineer
Builds
System-on-Chip (SOC) physical designs
Domain
Semiconductor / VLSI Design
Required skills
floor-planning, partitioning, placement, clock tree synthesis, routing, physical verification (LVS/DRC/ERC/Antenna), equivalence checks, static timing analysis (STA), crosstalk delay analysis, noise analysis, power optimization, timing and functional ECO implementation, congestion resolution, formal verification
Preferred skills
experience with Innovus, Encounter, ICC, Caliber, LEC, Primetime
Technologies
Innovus, Encounter, ICC, Caliber, LEC, Primetime
Responsibilities
Perform block-level floor-planning, partitioning, placement, and clock tree synthesis; Execute routing and physical verification (LVS/DRC/ERC/Antenna); Conduct equivalence checks, STA, crosstalk, noise, and power optimization; Implement timing and functional ECOs; Resolve congestion and timing closure issues; Guide team members and work in a global environment
Seniority
Staff, hands-on IC with mentorship
