Staff Design Engineer
Core
Lead physical design activities for SOC chips, covering floor-planning, partitioning, placement, clock tree synthesis, routing, and physical verification.
Role type
Staff Design Engineer (Physical Design)
Builds
System-on-Chip (SOC) physical designs
Domain
Semiconductor / VLSI Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Floor-planning, partitioning, placement, clock tree synthesis, routing, physical verification (LVS/DRC/ERC/Antenna), equivalence checks, static timing analysis (STA), crosstalk delay analysis, noise analysis, power optimization, timing and functional ECO implementation, congestion resolution, formal verification
Preferred skills
Experience with Innovus, Encounter, ICC, Caliber, LEC, Primetime
Responsibilities
Meet congestion, timing, and area metrics; implement ECOs; guide team members in global teams; resolve congestion and achieve timing closure
Seniority
Staff, hands-on IC with mentorship