Physical Design Engineer
Core
Implements custom IP and SoC designs from RTL to GDS, ensuring designs are ready for manufacturing.
Role type
Senior IC physical design engineer
Builds
Custom IP and System-on-Chip (SoC) designs
Domain
Semiconductor / VLSI physical design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (GDS design databases)
Required skills
Physical design flow (synthesis, place & route, CTS, floor planning, STA), signoff verification (formal equivalence, DRC, LEC, ERC, power integrity), EDA tools, scripting (Perl, TCL, Python), HDLs (VHDL, Verilog), timing closure, power/area optimization, DFT, mentoring
Preferred skills
Multiple clock domain design, power management, low power design methodologies, UPF specifications
Technologies
EDA tools, Perl, TCL, Python, VHDL, Verilog
Responsibilities
Perform physical design implementation from RTL to GDS; conduct synthesis, place and route, clock tree synthesis, floor planning, and static timing analysis; perform verification and signoff including formal equivalence, DRC, LEC, and power integrity analysis; analyze results and recommend fixes for violations; optimize designs for power, frequency, and area; mentor junior team members
Seniority
Senior, hands-on IC