Senior Physical Design Engineer
Core
Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database ready for manufacturing.
Role type
Senior Physical Design Engineer
Builds
Custom IP and System-on-Chip (SoC) designs
Domain
Semiconductor / Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Physical design flow (synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution), Signoff verification (formal equivalence, STA, reliability, power integrity, LEC, DRC, ERC), EDA tools, Scripting (Perl, TCL, Python), Hardware description languages (VHDL, Verilog), Tape-out experience in deep submicron nodes, Mentoring
Preferred skills
Multiple clock domains and clock/power management, Low power design, Power intent UPF specifications
Technologies
EDA tools, Perl, TCL, Python, VHDL, Verilog
Responsibilities
Conduct physical design flow including synthesis, place and route, clock tree synthesis, floor planning, and static timing analysis; Perform verification and signoff including formal equivalence, static timing analysis, reliability verification, and layout verification; Analyze results and make recommendations to fix violations; Optimize design for power, frequency, and area; Participate in developing physical design methodologies and flow automation
Seniority
Senior, hands-on IC
