Principal Engineer - Standard Cell Design
Core
Define next-generation standard cell library architecture, DTCO, and design methodology to deliver high-performance, low-voltage silicon for CPU, GPU, and emerging architectures.
Role type
Principal Engineer - Standard Cell Design
Builds
Scalable standard cell libraries and design methodologies for Intel foundry customers
Domain
Semiconductor / Advanced Process Nodes / Standard Cell Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production ML models (Incorrect mapping in thought, correcting to: physical/clinical work -> infrastructure/physical work context) -> infrastructure (Standard Cell Libraries)
Required skills
MOSFET electrical characteristics, transistor device physics, standard cell circuit design, PPA optimization, Vmin behavior, Spice simulation, low-power/high-performance techniques, clocking and sequential elements
Preferred skills
Technical leadership, local layout effect management, block-level design tool feedback, compact modeling, EDA tool interaction, cross-org technical alignment
Technologies
Spice, EDA tools, Standard Cell Libraries
Responsibilities
Shape standard cell library strategy and content definition; Drive circuit innovation for high-performance/low-voltage operation; Lead PPA and Vmin optimization; Interface with foundry customers for co-optimization; Partner with DTCO and product teams; Mentor circuit designers and technical leaders; Develop circuit methodology and validation frameworks; Analyze silicon and design data for improvements.
Seniority
Principal, strategy & mentorship