Staff / Senior Staff CAD & Methodology Engineer (Digital Implementation & Signoff)
Core
Architecting and optimizing automated RTL-to-GDSII physical design and timing signoff flows for AI accelerator architectures.
Role type
Staff CAD & Methodology Engineer (Physical Design & STA)
Builds
Automated physical design and signoff flows for AI hardware accelerators
Domain
Semiconductor physical design, Static Timing Analysis (STA), AI hardware
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Cadence Innovus, Cadence Tempus, Tcl, Python, floorplanning, placement, Clock Tree Synthesis (CTS), routing, power grid implementation, Static Timing Analysis (STA), DRC, electromigration, IR drop, version control (Git/Perforce)
Preferred skills
Deep sub-micron physical design concepts, Distributed Multi-Scenario Analysis (DMSA), automated ECO flows, tool evaluation and beta testing
Technologies
Cadence Innovus, Cadence Tempus, Python, Tcl, Makefile, Git, Perforce
Responsibilities
Architect and maintain automated physical design and signoff flows; Optimize Innovus recipes for floorplanning, placement, CTS, routing, and power grid; Own STA and timing signoff methodology using Tempus; Develop Python and Tcl automation to reduce tool runtime; Act as technical liaison with Cadence for tool evaluations and bug resolution; Mentor junior engineers on tool usage and flow mechanics
Seniority
Senior, hands-on IC
