Coherent Fabric Design
Core
Designing highly scalable, configurable, flexible, high-performance mesh interconnect IP for hyperscale AI infrastructure, IoT, and Automotive line of business.
Role type
Senior IC RTL logic design engineer (system IP coherent interconnect)
Builds
System IP Coherent Interconnect designs (mesh topology) for Arm's hyperscale, AI, IoT, and Automotive business units
Domain
Semiconductor / Hardware Design / System IP
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog RTL coding, fabric and interconnect design, high-speed interfaces (AMBA CHI, AXI), low-power design techniques, simulation and debug tools, Perl/Ruby scripting, Unix/Linux shells
Preferred skills
PCI Express (PCIe), Ethernet, DDR, transaction ordering, virtualization, MMUs, cache coherence, host bridge functions, Lint, synthesis, static timing, DFT, physical design methods
Technologies
SystemVerilog, AMBA CHI, AXI, PCIe, Ethernet, DDR, Perl, Ruby, Unix/Linux
Responsibilities
Logic design using SystemVerilog RTL coding, planning and tracking tasks to meet milestones, collaborating with verification and power teams to debug functional/performance issues, improving design methodology across the System IP group
Seniority
Senior, hands-on IC