SOC Timing Engineer
Core
Responsible for timing closure and signoff of FPGA/SoC and Subsystem timing, including static timing analysis and deriving interface timing constraints.
Role type
STA design engineer
Builds
FPGA/SoC and Subsystem designs
Domain
Semiconductor physical design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Static timing analysis, industry standard EDA tools (Primetime/PTPX), timing constraints, clocking, PVT analysis, tapeout experience in 10nm or lower technology
Technologies
Primetime, PTPX
Responsibilities
Perform static timing analysis, provide/derive interface timing constraints to partitions, conduct final timing signoff, work with design and architecture team for timing convergence analysis, collaborate with physical design team for timing closure
Seniority
Mid-level IC engineer
