Physical Design Methodology Engineer, AI HW IP
Core
Develops, deploys, and owns the RTL-to-GDSII methodology for AI hardware IP physical design teams to ensure new blocks start from a working flow.
Role type
Senior IC physical design methodology engineer (AI HW IP)
Builds
Production-ready RTL-to-GDSII flows for AI accelerators and high-performance CPUs
Domain
Semiconductor physical design, AI hardware IP, advanced nodes (FinFET/GAA)
Deliverable
production ML models | infrastructure
Required skills
Physical design methodology, CAD flow development, EDA automation, Tcl, Python, Perl, UPF/CPF, clock tree synthesis, signoff (EM/IR, DRC/LVS), PDK qualification
Preferred skills
AI/ML-driven flow optimization, EDA vendor partnership, multi-variant IP delivery
Technologies
FusionCompiler, ICC2, Innovus, Genus, PrimeTime, RedHawk
Responsibilities
Develop and support physical design methodology or CAD flows in production use, build flows for new technology nodes/PDKs/foundry targets, qualify new EDA releases, document flows for team autonomy
Seniority
Senior, hands-on IC
