Principal Subsystem Engineer (Design or DV)
Core
Lead the design or design verification of complex, high-performance custom IP and System on Chip (SoC) subsystems, focusing on AI/ML SoCs and delivering silicon from concept through bring-up.
Role type
Principal Subsystem Engineer (Design or DV)
Builds
Custom Intellectual Property (IP) and System on Chip (SoC) designs
Domain
Semiconductor / Hardware Engineering / AI/ML SoCs
Deliverable
production ML models | product features
Required skills
RTL coding (Verilog/System Verilog), UVM, Python/Perl scripting, microarchitecture specification, CDC/Lint closure, DFT implementation, static checks, simulation/emulation debugging, NoC/AMBA AXI/CHI protocols, power/performance tradeoffs
Preferred skills
Experience with AI/ML SoCs, debugging register transfer level designs, floor-planning awareness
Technologies
Verilog, System Verilog, C++, UVM, Python, Perl, AMBA AXI, CHI, NoC
Responsibilities
Technically lead one or more Subsystems as a design or DV engineer, collaborate on vertical and horizontal reuse of components, work with Architecture, Design, DV, PD, DFT, firmware, and post-silicon teams to debug system-level issues, drive synthesis, timing constraints, and performance tuning
Seniority
Principal, hands-on IC with mentorship
