Senior Staff / Principal SOC Floorplan Lead
Core
Own the physical foundation of next-generation AI and Data Center SoCs, bridging architecture, logic design, and physical design to achieve best-in-class Power, Performance, and Area (PPA).
Role type
Senior Staff / Principal SoC Floorplan Lead
Builds
High-performance, large-scale AI/Data Center chips on advanced process nodes (5nm, 3nm or below)
Domain
Semiconductor Physical Design (SoC Floorplanning) for AI and Data Center
Deliverable
production ML models
Required skills
SoC-level floorplanning, block partitioning, bump planning, flip-chip package co-design, analog/mixed-signal IP integration, high-speed SerDes routing, power delivery network design, macro placement, Tcl/Python scripting, Cadence Innovus
Preferred skills
multi-die/chiplet integration (2.5D, 3D packaging, UCIe), advanced clocking architectures (H-trees, meshes), Perl/Makefile automation
Technologies
Cadence Innovus, Tcl, Python, Perl, Makefile
Responsibilities
Own SoC-level floorplan from concept to tape-out; Partner with Architecture and RTL teams for block partitioning and data-flow planning; Lead bump planning and IO ring definition; Manage placement and custom routing for AMS IPs and SerDes; Design and analyze top-level power grids; Manage macro placement and pin assignments; Build scalable floorplanning workflows and scripts
Seniority
Senior Staff / Principal, hands-on IC
