AI-Driven ASIC Physical Design Principal Engineer
Core
Principal AI engineer building agentic physical design workflows and LLM-based copilots to automate ASIC physical design tasks like placement, routing, and timing analysis.
Role type
Principal IC AI/ML engineer (ASIC Physical Design)
Builds
Autonomous PnR workflows, RAG pipelines for design rule knowledge, and MCP wrappers connecting LLMs to EDA tools.
Domain
Semiconductor hardware design (ASIC) + Generative AI
Deliverable
production ML models | product features
Required skills
ASIC physical design (PnR, timing, congestion), Python, LLM prompting & agentic workflows, MCP (Model Context Protocol), EDA tool integration (Innovus, ICC2, Calibre), Docker/containerization, Machine Learning for placement/routing, Vector databases (Pinecone, Weaviate), Tcl scripting.
Preferred skills
RTL2GDSII flow, tapeout experience (7nm/5nm/3nm), EDA tools (Tempus/Primetime, Redhawk/Voltus, Pegasus).
Responsibilities
Identify high-value automation targets for physical design; Evaluate and benchmark LLM outputs against ground truth; Build agentic PnR workflows where AI iterates autonomously; Create RAG pipelines indexing internal PDKs and design rules; Write Tcl bridge scripts for EDA tool execution; Develop prompt architectures for interpreting STA/DRC/power reports.
Seniority
Principal, hands-on IC