Digital Design Engineer – AI Accelerators
Core
Design and implement high-throughput compute datapaths and microarchitectures for AI accelerator chips, integrating compute blocks with memory interfaces.
Role type
Senior IC digital design engineer (AI accelerators)
Builds
AI accelerator chips for neural network inference and training
Domain
Semiconductor / AI Hardware
Deliverable
production ML models | product features
Required skills
RTL design (SystemVerilog/Verilog), microarchitecture design, pipelined datapath design, memory hierarchy design, EDA tool usage (synthesis, STA, linting), hardware verification
Preferred skills
AI/ML accelerator design, Python for hardware modeling (Cocotb/PyRTL), quantization techniques, ML framework knowledge (PyTorch/TensorFlow), compiler stack familiarity
Technologies
SystemVerilog, Verilog, Questa, SpyGlass, Design Compiler, AXI, SRAM, PyTorch, TensorFlow, Cocotb, PyRTL
Responsibilities
Architect and implement high-throughput compute datapaths for neural network primitives; Integrate compute blocks with SRAM banks, register files, and external memory interfaces; Collaborate with compiler and ML teams to map models onto hardware efficiently; Implement RTL with a focus on modular, parameterized, and reusable design; Perform verification tasks including testbench support, functional checks, and debug; Drive lint, synthesis, and STA flows to ensure timing closure
Seniority
Mid-level, hands-on IC
