Principal Engineer, High‑Speed RTL Design
Core
Design and implement timing-critical high-speed RTL blocks for memory and storage solutions, ensuring robust logic for synthesis and timing closure.
Role type
Principal Engineer, High-Speed RTL Design
Builds
Memory and storage ICs (DRAM, NAND, NOR) for data centers, AI, 5G, and mobile applications
Domain
Semiconductor / Digital IC Design
Deliverable
production ML models | product features
Required skills
SystemVerilog, Verilog, FSM design, Clock-domain crossing (CDC), Reset synchronization, Setup/hold timing analysis, Multi-mode logic design, DFT-friendly RTL practices, UPF, LEC
Preferred skills
PMICs, mixed-signal SoCs, Python/Tcl scripting, RTL-DV-PD handshakes, AI-enabled engineering tools
Technologies
SystemVerilog, Verilog, UPF, LEC, Synthesis tools, Static Timing Analysis (STA) tools
Responsibilities
Design timing-critical RTL blocks (FSMs, register banks, telemetry); Implement clocking, reset, and power-aware logic; Integrate RTL into subsystems and debug using simulation; Collaborate with verification engineers to resolve timing and logic issues; Participate in design reviews and maintain documentation.
Seniority
Principal, hands-on IC design with strategic ownership
