Principal Subsystem Design Manager
Core
Lead the design of premium-quality custom Intellectual Property (IP) and System on Chip (SoC) subsystems, focusing on architectural and micro-architectural functions for high-performance, efficient execution.
Role type
Principal Subsystem Design Manager (IC)
Builds
Custom IP and SoC designs for complex, high-performance functions
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features
Required skills
Microarchitecture specification, RTL coding (Verilog/System Verilog), Synthesis, Timing constraints, PPA trade-offs, Post-silicon debug, Cross-functional team leadership, IP/SS design for CPUs/VPUs/GPUs/DMA/Tensor units, AI/ML SoC experience, Scripting (Python/Perl), Design quality checks, DFT implementation
Preferred skills
Experience with vertical/horizontal component reuse, Agile methodologies, Mentorship of engineering teams
Technologies
Verilog, System Verilog, Python, Perl
Responsibilities
Build, hire, and mentor a team of engineers; Technically lead one or more Subsystems; Interact with architects to develop micro-architectural specifications; Work with DV engineers to execute designs; Collaborate on component reuse; Provide technical leadership through mentorship and collaboration
Seniority
Principal, hands-on IC with strategic team leadership
